我问的问题可能太简单了，没有人理：改这里
PLL_CON register controls the operation of each PLL. If ENABLE bit is set, the corresponding PLL generates output after PLL locking period. The MDIV, PDIV, and SDIV values control the output frequency of PLL. The PLL also generates the output frequency when MDIV, PDIV, and VSEL are changed. However, the PLL locking period is not applied if only SDIV is changed. PLL Control Registers (APLL_CON0/APLL_CON1, R/W, Address = 0xE010_0100/0xE010_0104)
